1. Field of the Invention
This invention relates to processes for making integrated circuits and more particularly to processes which employ lift-off techniques. More specifically, the invention relates to processes for making self-aligned memory cells which form a very high density memory array.
2. Description of the Prior Art
Integrated circuits, particularly those employing field effect transistors in a semiconductor substrate, have achieved very high densities of active and passive components. To achieve these high densities various techniques and processes have been developed to reduce the size of each circuit and to reduce the area required for isolation within the substrate between the circuits. Moreover, in order to further increase the densities in the integrated circuits, for example, in the memory technology, very simple circuits have been developed which utilize a very small amount of surface area on the semiconductor substrate. One of the simplest circuits for providing a memory cell is described in commonly owned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. This cell employs a single field effect transistor as a switch for coupling a capacitor to a bit/sense line. In also commonly owned U.S. Pat. Nos. 3,811,076, by W. M. Smith, and 3,841,926, by R. H. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one device field effect transistor memory cell of the type described in the above-identified Dennard patent which utilizes a layer of polycrystalline silicon as a field shield and as an electrode for a storage capacitor in order to improve cell density. To further improve the density of the cells described in U.S. Pat. Nos. 3,811,076 and 3,841,926, the process for making the cells utilizes a dual layer of silicon nitride and silicon dioxide and a polysilicon conductive layer.
In U.S. Pat. Nos. 3,771,147, filed Dec. 4, 1972, there is disclosed a one device field effect transistor memory cell wherein a first level metal, tungsten, is used to provide a self-aligned gate and a metallic layer held at a reference potential serves as an electrode for the storage capacitor.
In U.S. Pat. No. 3,648,125, filed Feb. 2, 1971, there is disclosed a process for making integrated circuits which includes forming electrically isolated pockets by a grid of oxidized silicon extending into silicon material, and in the periodical, Electronics, Sept. 11, 1972, page 31, there is a suggestion that the use of oxide isolation techniques be employed for making single transistor memory cells.
Electrical isolation techniques wherein a polysilicon grid is used to produce islands of single crystal silicon is disclosed in U.S. Pat. No. 3,736,193, filed July 29, 1969.
Field effect transistors having silicon gates with a nitride-oxide gate dielectric are suggested in U.S. Pat. No. 3,699,646, filed Dec. 28, 1970, and in the periodical, Electronics, dated Aug. 2, 1971, on page 74.
In IBM Technical Disclosure Bulletin, Vol. 18, No. 1, June 1975, pages 68 and 69, there is described a memory array having a high word line packing density by employing spaced polysilicon lines which are oxidized with aluminum strips disposed between and insulated from the polysilicon lines.
Commonly assigned U.S. Pat. No. 3,849,136, filed on July 31, 1973, by K. R. Grebe, describes a lift-off process employing a photoresist for depositing in a controlled manner a thin film on a substrate.
In commonly assigned application Ser. No. 617,462 filed on Sept. 29, 1975, by A. Furman, H. L. Kalter and J. W. Nagel, now U.S. Pat. No. 4,021,789 there is disclosed a high density memory array employing a nitride-oxide gate dielectric and two layers of doped polycrystalline silicon separated only by a layer of oxide.
In IBM Technical Disclosure Bulletin, Vol. 18, No. 6, November 1975, pages 1766 and 1767, there is described an integrated circuit fabrication process utilizing a photoresist lift-off technique for forming a polysilicon layer and a platinum layer on an insulating layer of silicon dioxide wherein the platinum layer serves as the gate electrode for a field effect transistor.
By employing the techniques disclosed in the above indentified patents and articles, the semiconductor industry has produced integrated semiconductor circuits which contain thousands of cells on small semiconductor substrates or chips, which are generally made of silicon.